An Efficient Architecture for Signed Carry Save Multiplication

Abstract

The performance of a digital signal processing (DSP) system is greatly affected by the performance of its multiplication operations. Simultaneous improvement in performance metrics such as delay, power, area, and energy efficiency is difficult to achieve and is a challenge to be addressed. To this end, an efficient carry save multiplier (CSM) that employs modified square root carry select adder (MSCA) for the vector-merging addition and improved full adder (IFA) in place of conventional full adder is proposed. Among 16 x 16 multipliers, the critical path delay (CPD), power, area, power delay product (PDP), and  area delay product (ADP) of the proposed CSM are improved by 27.74, 19.4, 46.2, 41.4, and 60.87 percent respectively in comparison with improved booth multiplier and by 46.43, 31.46, 36.9, 63.05, and 65.96 percent respectively in comparison with low PDP booth multiplier. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.