ENERGY-EFFICIENT VLSI DESIGN STRATEGIES FOR NEXT-GENERATION DIGITIZED CMOS SYSTEMS: A MACHINE LEARNING APPROACH

Abstract

Low-power design-related features and uses aim at minimizing dynamic as well as static power consumption within an integrated circuit. The brief explanation is that development process along with dynamic technology is carrying concerns with respect to power consumption in a Very Large Scale IC. The more modernized digitized CMOS systems have made everyone turning toward the more energy-efficient designs. Therefore, this paper will address new approaches to lowering power consumption in VLSI circuits through machine-learning techniques. An evaluation of ML algorithms used for power optimization, their influence on design efficiency, and the focus on emerging trend-shifts in an energy-friendly VLSI design. The study further describes the challenges and trade-offs that need to be addressed in order to implement ML optimization techniques for next-generation CMOS systems.